
library IEEE;
use IEEE.std_logic_1164.all;

entity display_char is
	port (	clk			: in	std_logic;	
		reset			: in	std_logic;
		
		char0		: in character;
		char1		: in character;
		char2		: in character;
		char3		: in character;

		display_data	: out	std_logic_vector (7 downto 0);
		display_enable	: out	std_logic_vector (3 downto 0)
	);
end entity display_char;



architecture structural of display_char is

	component display_controller is
		port (	clk			: in	std_logic;	
			reset			: in	std_logic;
			display_data_mux_sel	: out	std_logic_vector (1 downto 0);
			display_enable		: out	std_logic_vector (3 downto 0)
		);
	end component display_controller;




	component mux_char_4input is
		port (	input_0			: in	character;
			input_1			: in	character;
			input_2			: in	character;
			input_3			: in	character;
			sel			: in	std_logic_vector (1 downto 0);
			output			: out	character
		);
	end component mux_char_4input;


	component char2seg7 is
		port (	bin			: in	character;
			seg7			: out	std_logic_vector (7 downto 0)
		);
	end component char2seg7;


	signal	display_data_mux_sel		: std_logic_vector (1 downto 0);
	signal	sel_bin_display_data		: character;
	signal	seg7_display_data		: std_logic_vector (7 downto 0);

begin

lblctrl:	display_controller port map (	clk			=> clk,	
					reset			=> reset,
					display_data_mux_sel	=> display_data_mux_sel,
					display_enable		=> display_enable
			);
	

lblsel:	mux_char_4input	port map (	input_0			=> char0,
					input_1			=> char1,
					input_2			=> char2,
					input_3			=> char3,
					sel			=> display_data_mux_sel,
					output			=> sel_bin_display_data
			);

lblface:	char2seg7	port map (	bin			=> sel_bin_display_data,
					seg7			=> display_data
			);


end architecture structural;


